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? vitesse seiconductor corporation page 1 vs8021/8022 data sheet 2.5 gbits/sec sonet compatib le 8-bit mux/demux chipset g52028-0 rev. 4.0 vitesse features functional description the vs8021 and vs8022 are high speed sonet interf ace de vices capable of handling serial data at rates up to 2.5 gbits/second. these products can be used for sts-3 through sts-48 sonet applications. these products are fabricated in gallium arsenide using the vitesse h-gaas ? e/d mesfet process which achie v es high speed and lo w po wer dissipation. these products are packaged in a ceramic 52-pin leaded ceramic chip carrier. vs8021 the vs8021 contains an 8:1 multiplexer and a self-positioning timer. the 8:1 multiplexer accepts 8 parallel dif ferential ecl data inputs ( d1-d8, d1n-d8n ) at rates up to 312.5 mbits/sec and multiple x es them into a serial differential bit stream output (do, don) at rates up to 2.5 gbits/sec. the internal timing of the vs8021 is b uilt around the high speed clock (up to 2.5 ghz) deli v ered onto the chip through a differential input (clki, clkin). this signal is subsequently echoed at the high speed dif feren- tial output (co, con). the parallel data inputs are clock ed to on-chip input re gisters with an e xternally supplied dif ferential ecl input ( byclk, byclkn ) operating at the same rate as the data inputs. an internal byte clock, which is a di vide by 8 v ersion of the high speed clock, is used to transfer the data to a set of b uffer registers. this internal byte clock is brought off chip at the ecl output clk8, clk8n. internal circuitry monitors the internal and e xternal byte clocks and generates an err signal if a timing violation is detected. this signal can be gated to the sync input which is edge sensitive high. an active sync input allows the vs8021 timing to shift, positioning it properly against the external byte clock, clk8, clk8n. when a clk8 timing switch is made, normal data ow will be invalid for 1 byte. there are two clock inputs, namely the clki and byclk, going into the vs8021. these two clocks serve as timing references for dif ferent parts of the vs8021. the byclk is used to trigger the input re gisters for the parallel data inputs, while the clki is used to trigger the high speed serial output re gister as well as some of the timing circuitry for the parallel to serial con v ersion. furthermore, in order to mak e this part easy to use, the user is not required to assume a known phase relationship between clki and the byclk. ? dif ferential or single-ended inputs and outputs ? low power dissipation: 2.3w (typ. per chip) ? standard ecl power supplies: vee = -5.2 v, vtt = -2.0 v ? available in commercial (0 to +70 c) or industrial (-40 to +85 c) t emperature ranges ? proven e/d mode gaas technology ? 52-pin leaded ceramic chip carrier ? serial data rates up to 2.5 gb/s ? parallel data rates up to 312.5 mb/s ? ecl 100k compatible parallel data i/os ? divide-by-8 clock for synchronization of parallel data to interfacing chips ? sonet frame recovery circuitry (vs8022) ? compatible with sts-3 to sts-48 sonet applications
vs8021/8022 vitesse data sheet 2.5 gbits/sec sonet compatible 8-bit mux/demux chipset page 2 ? vitesse semiconductor corporation g52028-0 rev. 4.0 an internal phase detector and phase adjust circuit are used to f acilitate the tw o asynchronous circuits to w ork with each other . the phase detector and the phase adjust circuit w ork together to adjust the internal clock clk8 to mak e sure the set up and hold conditions are met for the internal re gisters. clk8 is derived from clki and the rclk is a non-phase v arying byte clock output. the edge sensiti v e sync signal is simply the control signal that enables the phase detector circuitry. as a summary , the clki is the high speed clock input. the byclk is the e xternal byte clock. the clk8 is the internal byte clock deri v ed from clki, phase-adjusted if sync is enabled. the rclk is a non-phase- adjusted di vided-by-8 clock generated from clki. the phase of rclk, rclkn is not af fected by the self- adjusting circuitry , therefore it can be used as a system reference clock. rclk, rclkn can be used by the sys- tem designer to generate byclk, byclkn. the self-positioning timer and rclk, rclkn allow for the cre- ation of very tight parallel data timing for the vs8021. figure 1: vs8021 block diagram err phase adjustable byte clock output clk8 clk8n serial data output 8:1 multiplexer timing generator do don high speed clock inputs clki clkin byte clock inputs byclk byclkn high speed clock output co con independent byte clock output rclk rclkn phase detecto r buffer register 8 8 parallel data inputs d1 d1n d8 d8n input register phase adjust sync
? vitesse seiconductor corporation page 3 vs8021/8022 data sheet 2.5 gbits/sec sonet compatib le 8-bit mux/demux chipset g52028-0 rev. 4.0 vitesse vs8022 the vs8022 contains both a 1:8 demultiple x er and sonet frame reco v ery circuitry . the 1:8 demultiple xer accepts a serial data input ( di, din ) at rates up to 2.5 gbits/second and con v erts it into 8 parallel dif ferential ecl data outputs ( d1-d8, d1n-d8n ) at rates up to 312.5 mbits/sec. v alid parallel data outputs are indicated by the divide by 8 differential clock outputs bycko, byckon . the vs8022 also contains a sonet frame recovery circuit. the frame recovery circuits are enabled by a falling edge on the oofn ecl input when the fdis input is lo w . once enabled, the frame reco v ery circuit starts looking for the sonet framing sequence. once the frame is detected, the w ord boundary is realigned, a con rmation signal is sent of f-chip through the fp ecl output and the frame reco v ery circuits are disabled. while the frame aligner is hunting for the frame, bycko, byckon and parallel data are invalid. figure 2: vs8022 block diagram frame recovery circuits are disabled by frame detection (resulting in fp) or by a falling edge on the oofn input while fdis is high. parallel data outputs serial data in 1:8 demultiplexer timing generator high speed clock inputs ?frame detection signal di d1 clki clkin din d1n byte clock out bycko byckon fp d8 d8n sonet frame detection & recovery fdis oofn frame recovery disable frame recovery clock
vs8021/8022 vitesse data sheet 2.5 gbits/sec sonet compatible 8-bit mux/demux chipset page 4 ? vitesse semiconductor corporation g52028-0 rev. 4.0 vs8021 multiplexer ac characteristics (over recommended operating conditions) note: (1) the parts are guaranteed by design to operate from dc to a maximum frequency of 2.5 ghz. (2) required when sync not connected to err figure 3: vs8021 multiplexer waveforms parameter description min typ max units t c (1) clock period 400 - - ps t d byte clock period (t d = t c x 8) 3.2 - - ns t dsu parallel data set-up time 0.6 - - ns t dh data hold time 1.4 - - ns t cmd high speed clock output (co, con) timing, falling edge of co to muxed data output, (do, don) timing 220 - 350 ps t bclk8 (2) byte clock to clk8 timing 0.5 1.0 1.5 ns jitter(pk-to-pk) clki, clkin to do, don (max-min), (hi to lo), same part, same pin at constant conditions - <50 - ps t d t c valid data(2) t dh serialized byte 1 d01 d02 d03 d04 d05 d06 d07 d08 t dsu valid data(1) t cmd notes: = don't care. period x 8 = period. clki (clkin) byclk (byclkn) (1) negative edge is active edge. (2) byclk/clk8 timing required when sync not connected to err. t bclk8 high speed differential clock input d1-d8, d1n-d8n co, con do,don byte clock input parallel differential data inputs high speed differential clock outputs high speed differential data outputs sync clk8 adjustment input clki , clkin (1) byclk (byclkn) (1) phase adjustable ? 8 output clk8 (2)
? vitesse seiconductor corporation page 5 vs8021/8022 data sheet 2.5 gbits/sec sonet compatib le 8-bit mux/demux chipset g52028-0 rev. 4.0 vitesse figure 4: vs8022 demultiplexer waveforms a1 a1 d1 (d1n) d2 (d2n) d3 (d3n) d4 (d4n) d5 (d5n) d6 (d6n) d7 (d7n) d8 (d8n) t pfp a2 a2 a2 data data data data valid data valid data valid data valid data valid data valid data valid data valid data valid data valid data valid data valid data valid data valid data valid data valid data fp parallel data? output summary t dfp demultiplexed parallel data outputs t c a1 a1 a1 a2 a2 a2 data t oofn t oofnpw sonet sts-3 framing sequence data data data data t bd resynch bycko t d clki (clkin) oofn di (din) bycko (byckon) high speed differential clock input frame recovery clock input high speed serial data inputs frame detection confirm output byte clock output (1) 1) negative edge is active edge. 2) the parallel data outputs only begin showing valid data after the last a2 of the sonet framing sequence. the example waveforms shown above use an sts-3 framing sequence for convenience, thus valid data is output after the third a2 in the sequence. = don't care. notes: (2)
vs8021/8022 vitesse data sheet 2.5 gbits/sec sonet compatible 8-bit mux/demux chipset page 6 ? vitesse semiconductor corporation g52028-0 rev. 4.0 vs8022 demultiplexer ac characteristics (over recommended operating conditions) note: if t c changes, all the remaining parameters change as indicated by the equations. vs8022 sonet frame recovery and detection the sonet framing sequence is a string of a1 bytes follo wed by a string of a2 bytes. (a1 = 11110110 and a2 = 00101000) the rst serial bit starts at the left of the byte. the table belo w sho ws the number of a1 and a2 bytes in each sonet frame for dif ferent line rates. the vs8022 contains a frame reco v ery circuit and a frame detection circuit.. frame recovery circuit the frame recov ery circuit is designed to scan the serial data stream, looking for the a1 byte. when it nds the a1 pattern, it adjusts internal timing so that the serial data is properly demultiple x ed onto the eight parallel outputs. subsequently , the msb of the a1 byte will appear in the d1 position and lsb of the a1 byte will appear in the d8 position. this w ord boundary alignment causes the byck o, byck on output to be resynchronized. while the frame aligner is hunting for the frame, bycko and parallel data are in valid. frame recov ery circuits are disabled by frame detection (resulting in fp) or by a falling edge on the oofn input while fdis is high. parameter description min typ max units t c clock period * 400 - - ps t d byte clock period (t d = t c x 8) (framed) 3.2 - - ns t bd byte clock output to valid data 0.5 1.0 2.0 ns t dfp fp rising edge from parallel data output change from a1 to a2 (t dfp = t d ) - 3.2 - ns t pfp fp pulse width (t pfp = t d ) 3.2 - - ns t oofn oofn falling edge before a1 changes to a2 (t oofn = t d x 4) 12.8 - - ns t oofnpw oofn pulse width (t oofnpw = t d ) 3.2 - - ns phase margin serial data phase timing margin with respect fo high speed clock: 135 180 - degrees sts level line rate (mb/s) # of a1 bytes # of a2 bytes sts-3 155.520 3 3 sts-12 622.080 12 12 sts-48 2488.32 48 48 1 t su t h + t c ------------------- - ? ? ? 360 phase margin =
? vitesse seiconductor corporation page 7 vs8021/8022 data sheet 2.5 gbits/sec sonet compatib le 8-bit mux/demux chipset g52028-0 rev. 4.0 vitesse frame detection circuit the frame detection circuit monitors the demultiple x ed data, and senses the boundary between a1 and a2 bytes. this pulse on the fp output will reset the frame reco v ery circuit, so that no further resynchronization will occur until permission is given through oofn. circuit operation the frame reco v ery circuits are initialized and enabled on the f alling edge of the oofn ecl input with fdis held lo w. the oofn must be at least one byte clock period wide. it must occur at least four byte clock periods before the a1/a2 boundary. the circuit requires at least three a1 bytes followed by 3 a2 bytes for suc- cessful alignment. the rst a1 byte is used by the frame reco v ery circuit to obtain initial w ord boundary align- ment, while the follo wing two a1 and three a2 bytes are used to reset the frame reco v ery circuit and maintain alignment for the subsequent bit stream. frame recognition will occur for each w ord boundary aligned a1a1a2a2a2 sequence in the data stream. frame recognition is signaled by a one byte clock period high pulse on the fp ecl output pin. this fp pulse will appear one byte period after the rst a2 byte appears on the paral- lel data output pins. 3 a1s 3 a2s 3 c1s 9 rows data 3 x 3 bytes 3 x 90 bytes 125 m s transport overhead sts-3 envelope capacity 48 a1s 48 a2s 48 c1s 9 rows data 3 x 48 bytes 48 x 90 bytes 125 m s transport overhead sts-48 envelope capacity note: a1s and a2s: sonet framing sequence c1s: sts frame id sts-3 frame sts-48 frame
vs8021/8022 vitesse data sheet 2.5 gbits/sec sonet compatible 8-bit mux/demux chipset page 8 ? vitesse semiconductor corporation g52028-0 rev. 4.0 absolute maximum ratings (1) power supply voltage ( v tt ) ...........................................................................................................-3.0v to + 0.5v power supply voltage ( v ee ) ....................................................................................................v tt + 0.7v to -6.0v ecl input voltage applied (2) ( v eclin ) ...........................................................................................-2.5v to + 0.5v high speed input voltage applied (2) ( v hsin ).....................................................................v ee -0.7v to v cc + 0.7v output current (dc, output high) ( i out ) ..................................................................................................-50 ma case temperature under bias ( t c ) ................................................................................................ -55 o to + 125 o c storage temperature (3) ( t stg ) ........................................................................................................ -65 o to + 150 o c recommended operating conditions ecl power supply voltage (4) ( v tt ) ...................................................................................................-2.0v 0.1v power supply voltage ( v ee ) .............................................................................................................-5.2v 0.26v operating temperature range (3) ( t ) ....................................(commercial) 0 o to 70 o c, (industrial) -40 o to + 85 o c notes: (1) caution: stresses listed under ?bsolute maximum ratings?may be applied to devices one at a time without causing permanent damage. functionality at or exceeding the values listed is not implied. exposur e to these values for extended periods may affect device reliability. (2) v tt must be applied before any input signal voltage magnitude ( v eclin and v hsin ) can be greater than v tt -0.5v. (3) lower limit of speci?ation is ambient temperature and upper limit is case temperature. (4) when using internal ecl 100k reference level.
? vitesse seiconductor corporation page 9 vs8021/8022 data sheet 2.5 gbits/sec sonet compatib le 8-bit mux/demux chipset g52028-0 rev. 4.0 vitesse dc characteristics table 1: low speed ecl inputs and outputs (over recommended operating range with internal v ref, v cc = gnd, output load = 50 w to -2.0v) note: differential ecl output pins must be terminated identically. table 2: power dissipation (over recommended operating conditions, v cc = gnd, outputs open circuit) table 3: high speed inputs and outputs (over recommended operating conditions, v cc = gnd, output load = 50 w to -2.0v) notes: 1) a reference generator is built in to each high speed input, and these inputs are designed to be ac coupled. 2) if a high speed input is used single-ended, a 150 pf capacitor must be connected between the unused high speed or com- plement input and the power supply (v tt ). 3) differential high speed outputs must be terminated identically. 4) esd pr otection is minimal for the high speed input pins, ther efore, proper procedur es should be used when handling this product parameter description min typ max units conditions v oh output high voltage -1020 - -700 mv v in = v ih (max) or v il (min) v ol output low voltage v tt - -1620 mv v in = v ih (max) or v il (min) v ih input high voltage -1150 - -600 mv guaranteed high signal for all inputs v il input low voltage v tt - -1500 mv guaranteed low signal for all inputs d v out output voltage swing 0.8 1.0 1.4 v output load 50 w to v tt parameter description vs8021 (min) vs8021 (typ) vs8021 (max) vs8022 (min) vs8022 (typ) vs8022 (max) units i ee power supply current from v ee - 400 600 - 450 600 ma i tt power supply current from v tt - 110 200 - 120 200 ma p d power dissipation 2.3 3.75 - 2.6 3.75 w parameter description min typ max units conditions d v in input voltage swing 0.8 1.0 1.2 v ac coupled v oh output high voltage - -0.9 - v output load, 50 w to -2.0v v ol output low voltage - -1.8 - v output load, 50 w to -2.0v d v out(data) output voltage swing for data 0.6 0.8 1.2 v output load, 50 w to -2.0v d v out(clk) output voltage swing for clock 0.6 0.7 1.2 v output load, 50 w to -2.0v
vs8021/8022 vitesse data sheet 2.5 gbits/sec sonet compatible 8-bit mux/demux chipset page 10 ? vitesse semiconductor corporation g52028-0 rev. 4.0 high speed inputs in the past, the high speed inputs, which are typically used for serial data and high speed clock inputs with frequencies greater than 1ghz, were speci ed with absolute minimum and maximum v oltage v alues. since these inputs are intended for a c coupled applications, the y hav e been re-speci ed in terms of a v oltage swing ( d v in ). high speed clocks are intended for a c coupled operation. in most situations high speed serial data will have high transition density and contain no dc offsets, making them candidates for ac coupling as well. how- ever, it is possible to employ dc coupling when the serial input data contains a dc component. the structure of the high speed input circuit is sho wn below . dc coupled circuits may be used to operate this input pro vided that the input swing is centered around the reference v oltage. since the internal resistor divider which forms the -3.5v reference presents an attenuation factor of only 0.6 to the v ee power supply, it is recommended that, in single-ended dc coupling situations, the user pro vide an e xternal reference which has better temperature and po wer supply rejection than the simple on chip resisti ve attenuator. this external refer- ence should ha v e a nominal v alue of -3.5 v and can be connected to the complimentary input. this complication can be avoided in dc coupled situations by using differential signals. 50 w chip boundary -3.5 v -3.5 v v cc = gnd v ee = -5.2v 150 pf v tt v tt r ? 1k w 150 pf
? vitesse seiconductor corporation page 11 vs8021/8022 data sheet 2.5 gbits/sec sonet compatib le 8-bit mux/demux chipset g52028-0 rev. 4.0 vitesse example application: sts-48 sonet system link the objectiv e in this e xample is to multiple x/demultiple x 8 channels at the sts-48 line rate with sonet frame recovery capability. the system can be implemented using the vs8021 and vs8022 as follows: 8:1 multiplexer data at a line rate of 311.04 mbytes/sec is re gistered at the inputs using the e xternally pro vided 311.04 mhz byte clock. err is gated into sync which is edge triggered for retiming of the input w ord. the 2488.32 mhz clock is used to generate timing signals for the mutiple xing function. the mux ed output at 2488.32 mbits/ sec is generated at the serial data output of vs8021. 1:8 demultiplexer the 1:8 demultiple x er recei v es serial data at 2488.32 mbits/sec and generates parallel data at 311.04 mbytes/sec along with a byte clock output of 311.04 mhz. the demux also has the sonet frame reco very and detection circuitry. during system start-up oofn input recei v es a f alling edge from the system control to permit reco very of the sonet frame and align on byte boundaries. once the frame is aligned, the fp pulse is generated on e very sonet frame. if for an y reason the fp pulse disappears on frame boundaries then this signals the system that the frame synchronization is lost. the system then asserts the oofn input (high to lo w) to reco v er the sonet frame and align on byte boundaries, bringing the system back to a synchronized condition. after syn- chronization is achieved, the fp pulse starts again on every frame. esd protection electrostatic dischar ge protection is pro vided for ecl i/o's and high speed clock and data i/o's to the fol- lowing minimum limits: ecl i/o ............................................................................................................ 1000v high speed clock and data inputs ..................................................................... 500v figure 5: sts-48 sonet system link sts = synchronous transport signal oc = optical carrier optic fiber vs8022 chip boundary d8/d8n d7/d7n d6/d6n d5/d5n d3/d3n d2/d2n d1/d1n d4/d4n 311.04 mhz byte clock out (bycko, byckon) frame enable (oofn) frame pulse (fp) sts-48 (di, din) 311.04 mbyte/sec data oc-48 optical reciever 1:8 demultiplexer timing generator sonet frame detection & recovery frame recovery disable (fdis) clock recovery high speed clock (co, con) oc-48 311.04 mbyte/sec data optical driver 311.04 mhz byte clock (byclk, byclkn) 2488.32 mhz high speed clock (clki, clkin) sts-48 (do, don) d1/d1n d2/d2n d3/d3n d4/d4n d5/d5n d6/d6n d7/d7n d8/d8n sync err clk8, clk8n 8:1 multiplexer timing generator rclk, rclkn vs8021 chip boundary
vs8021/8022 vitesse data sheet 2.5 gbits/sec sonet compatible 8-bit mux/demux chipset page 12 ? vitesse semiconductor corporation g52028-0 rev. 4.0 figure 6: vs8021 pin diagram nc nc nc vee do co con clkin vcc clki nc nc don (1) 33 32 d7 d6n d6 d5n d5 byclk d4n d4 vcc vtt vcc d3n err sync nc d2 d3 d2n vcc d1n d1 vee vcc clk8 clk8n heat sink side vs8021 27 28 29 30 31 34 35 36 37 38 39 52 51 50 49 48 47 46 45 44 43 42 41 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 byclkn nc nc nc nc rclk nc d8n d8 vcc vtt vcc d7n rclkn
? vitesse seiconductor corporation page 13 vs8021/8022 data sheet 2.5 gbits/sec sonet compatib le 8-bit mux/demux chipset g52028-0 rev. 4.0 vitesse table 4: vs8021 pin description. note: 1) pin #23 on both parts is connected to the heat sink. connect to vee or most negative chip voltage. pin # name i/o i/o type description 1-3, 34, 35, 37-42,47, 48, 50-52 d1-d8, d1n-d8n i ecl parallel ecl differential datas inputs 17, 19 clki, clkin i hs high speed differential clock inputs 44, 45 byclk, byclkn i ecl divide by 8 clock ecl input 22, 24 do, don o hs high speed serial data output 21, 20 co, con o hs high speed differential clock output 32, 31 clk8, clk8n o ecl phase adjustable clk ? 8 dif ferential ecl clock output 8, 6 rclk, rclkn o ecl independent clk ? 8 differential ecl clock output 29 err o ecl error detection ecl output 28 sync i ecl error correction ecl input 4, 10, 18, 30 ,36, 43, 49 v cc ground connection 7, 46 v tt -2.0v supply for internal reference generation & low power logic 23 (1) , 33 v ee -5.2v supply for high speed logic 5, 9, 11-16, 25, 26, 27 nc no connection
vs8021/8022 vitesse data sheet 2.5 gbits/sec sonet compatible 8-bit mux/demux chipset page 14 ? vitesse semiconductor corporation g52028-0 rev. 4.0 figure 7: vs8022 pin diagram table 5: vs8022 pin description note: 1) pin #23 on both parts is connected to the heat sink. connect to vee or most negative chip voltage. pin # name i/o i/o type description 3, 5, 6, 8, 31, 32, 34, 35, 38-40, 42, 48, 50-52 d1-d8, d1n-d8n o ecl parallel ecl differential data outputs 17, 19 clki, clkin i hs high speed differential clock inputs 47, 44 bycko, byckon o ecl divide by 8 clock ecl outputs 15, 16 di, din i hs high speed differential serial data inputs 11 fdis i ecl frame recovery disable input 12 oofn i ecl frame recovery enable ecl input 4, 10, 18, 30, 36, 43, 49 v cc i ground connection 7, 46 v tt -2.0v supply for internal reference generation & low power logic 23 (1) , 33 v ee -5.2v supply for high speed logic 1, 2, 13, 14, 20-22, 24- 29, 37, 41, 45 nc no connection nc d6 d6n vcc d7 d7n vee vcc nc nc d8 nc d8n di din nc vee nc nc nc clkin vcc clki nc nc nc (1) d2n d2 d1n d1 oofn nc vcc vtt fp vcc fdis nc nc d3 d3n d4 d4n bycko nc byckon d5 nc vcc vtt vcc d5n heat sink side vs8022 27 28 29 30 31 32 33 34 35 36 37 38 39 52 51 50 49 48 47 46 45 44 43 42 41 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
? vitesse seiconductor corporation page 15 vs8021/8022 data sheet 2.5 gbits/sec sonet compatib le 8-bit mux/demux chipset g52028-0 rev. 4.0 vitesse package information *at package body. item mm (min/max) in (min/max) item mm (min/max) in (min/max) a 18.54/19. 56 0.730/0.770 i 0.41/0.61 0.016/0.024 b 1.02/1.52 0.040/0.060 j 2.03/2.79 0.080/0.110 c* 15.49/16.51 0.610/0.650 k* 0.09/0.24 0.003/0.009 d* 15.24 typ 0.600 typ l 4.57/5.34 0.180/0.210 e 1.27 typ 0.050 typ m 27.69/30.22 1.090/1.190 f 0.76/1.02 0.030/0.040 n 0.36/0.56 0.014/0.022 g 16.94 typ 0.667 typ o 1.75/1.90 0.069/0.075 h 1.91/2.41 0.075/0.095 52-pin leaded ceramic package (ldcc) heat sink side package is cavity down 52 1 e 45 n o k c a i j m l b notes: drawing not to scale. packages: ceramic (alumina); heat sink: copper-tungsten; leads: alloy 42 with gold plating. d
vs8021/8022 vitesse data sheet 2.5 gbits/sec sonet compatible 8-bit mux/demux chipset page 16 ? vitesse semiconductor corporation g52028-0 rev. 4.0 dut boards the vs8021/vs8022 dut boards are special purpose circuit boards which pro vide a test bed suitable for ev aluating the performance characteristics of the vs8021 8:1 multiple x er or the vs8022 1:8 demultiple xer in the 52 pin ldcc package. the gure belo w is a schematic representation of these circuit boards. these boards pro vide a controlled impedance transmission line for all signals, and suitable decoupling for the po wer supplies. the signal traces hav e a characteristic impedance of 50 w . all ecl input lines are terminated with 50 w (chip resistor) as close to the de vice package pin as possible. the high speed inputs are also pro vided with 150pf blocking capacitors as shown. these capacitors are shorted in applications which require dc connection to these inputs. signals are launched onto the circuit board and remo v ed by means of sma coaxial connectors. while the input signals are terminated, the output signals are pro vided open circuit and are intended to be terminated in the measuring instrument such as an oscilloscope. normally , the vs8021 and vs8022 circuits operate in an ecl en vironment with standard ecl po wer buses: 0v, -2v, -5.2v . in order to simplify interf ace to standard ground referenced test equipment, ho wever, the circuit board power buses are offset so that the shield connectors are at ground voltage. the gure below shows the arrangement of the po wer supply decoupling capacitors. there is a 33 m f electrolytic capacitor , as well as several 0.01 m f ceramic capacitors across each po wer bus. the de vice to be tested is held in place with a pres- sure retaining xture. the gures on the following tw o pages indicate the ph ysical dimensions and the connec- tions labels for the evaluation boards. figure 8: vs8021/vs8022 dut board schematics high speed data or clock outputs: device under test v ee 50 w v cc 150 pf 0.01 m f 0.01 m f 0.01 m f 33 m f 33 m f + 2v - 3.2v ecl data or control inputs inp inp inp ecl data or clock outputs high speed clock inputs or high speed data inputs 50 w 50 w 0.01 m f 150 pf inp 50 w
? vitesse seiconductor corporation page 17 vs8021/8022 data sheet 2.5 gbits/sec sonet compatib le 8-bit mux/demux chipset g52028-0 rev. 4.0 vitesse figure 9: vs8021 dut dimensions and connection diagram d6n nc clki byclk d7 d6 d5n nc d8n rclkn rclk eye_sync test clkin nc don nc d1 d2 d2n d3 d3n nc sync err clk8n clk8 nc d5 byclkn 8.0" sq. do co con nc nc d8 d7n d4n d4 d1n v itesse vs8021 vcc vee vref vtt 0.75" typ 201-137-6 sma connector (typ)
vs8021/8022 vitesse data sheet 2.5 gbits/sec sonet compatible 8-bit mux/demux chipset page 18 ? vitesse semiconductor corporation g52028-0 rev. 4.0 figure 10: vs8022 dut dimensions and connection diagram vcc vee vref vtt d3n di clki byckon d3 d4 d4n d2 d2n d1n d1 fp fdis clkin nc nc nc d7n nc d6n d6 d5n nc nc nc d8n d8 oofn bycko nc 8.0" sq. nc nc nc din nc nc nc d5 nc d7 vs8022 v itesse 0.75" typ 201-136-0 sma connector (typ)
? vitesse seiconductor corporation page 19 vs8021/8022 data sheet 2.5 gbits/sec sonet compatib le 8-bit mux/demux chipset g52028-0 rev. 4.0 vitesse dut test setup t est equipment that is equal to or better than the follo wing is recommended for testing the vs8021 and vs8022 dut boards: 5 ghz oscilloscope 2.5 ghz bit error rate tester power supplies -3.2 v, 1 amp per board +2.0 v, 1 amp per board the gure below shows one possible test setup for the vs8021 and vs8022 dut boards. in this congura- tion the bit error rate t ester sends a clock and serial bit pattern into the vs8022 dut board. this data is demultiplex ed into a byte wide pattern which is transferred via matched cables to the vs8021 dut board where the byte wide data is multiple x ed into a serial bit stream which is sent into the error detector . the bit error rate tester will v erify that the bit stream that is sent out of the generator matches the bit stream that is fed back into the error detector . alw ays use matched delay cables between complementary signals and between data and clock signals. the oscilloscope can be used to vie w signal inte grity of v arious signals and to monitor rise and fall times. figure 11: vsc8021/8022 dut test setup oscilloscope trig bit error rate tester error detector pulse pattern generator sync output input clock pattern data clock clock data data vs8022 clock d1 d1n d7 d7n byclko byclkon di din clki vs8021 d0 d0n c0 c0n clki clk8 d1 d1n d7 d7n byclk err sync ch3 ch2 ch1 50 w byclkn +0.7v
vs8021/8022 vitesse data sheet 2.5 gbits/sec sonet compatible 8-bit mux/demux chipset page 20 ? vitesse semiconductor corporation g52028-0 rev. 4.0 ordering information v itesse products are a v ailable in a v ariety of packages and operating ranges. the order number for this product is formed by using a combination of the follo wing: device t ype, package t ype, and operating t em- perature range . notice v itesse semiconductor corporation reserv es the right to mak e changes in its products, speci cations or other information at an y time without prior notice. therefore the reader is cautioned to con rm that this datasheet is current prior to placing an y orders. the compan y assumes no responsibility for an y circuitry described other than circuitry entirely embodied in a vitesse product. warning vitesse semiconductor corporation s product are not intended for use in life support appliances, de vices or sys- tems. use of a vitesse product in such applications without the written consent is prohibited. vs80xx f i temperature c: commercial (0 to 70 c) i: industrial (-40 to +85 c) package type f: leaded chip carrier (ldcc) device type vs8021: sonet - 2.5 gb/sec 8-bit multiplexer vs8022: sonet - 2.5 gb/sec 8-bit demultiplexer

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